So true. The levels of indirection from a pointer to an actual DRAM chip address are insane.
Then there's the electrical bus: DDR5 runs so fast it need channel characterisation (sorta like the old model dial up sounds) on the lines between the controller and the DRAM. No more 5V and 0V for TTL signals there.
Training is the general description of the processes underlying both the DFE and the MBIST bios settings, which are usually separated into different sections; very broadly, the former (DFE) is the one most commonly thought of as DRAM Training and focuses the ‘physical’ layer training i.e. electrical characterization, while the latter (MBIST) configures how rigorously the channel’s ‘protocol’ layer training evaluates signal eyes tests over the physical transport.
You can draw an analogy for comprehension purposes between DFE and 1/2.5/5/10G auto-detection logic in Ethernet, which does various circuit-level characterization; and between MBIST and f3probe, which writes data and then reads it back in various algorithmic test patterns to ensure that the electrical training produced a usable result that can carry data as specified rather than just claiming to and then crashing later on.
Then there's the electrical bus: DDR5 runs so fast it need channel characterisation (sorta like the old model dial up sounds) on the lines between the controller and the DRAM. No more 5V and 0V for TTL signals there.